Field of the Invention
The invention relates to a semiconductor device, and more particularly to a standard cell.
Description of the Related Art
In recent years, the increasing speed and functionality of digital circuits has led to the speeding-up and integration of semiconductor integrated circuit devices. As a circuit grows in size, the layout of the semiconductor integrated circuit device is generally designed using a standard cell library.
A standard cell is a group of transistor and interconnect structures that provides a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flip-flop or latch). However, parasitic resistance in a standard cell layout can increase significantly in advanced process technology (e.g. FinFet technology). This is due to the increased resistive interconnections used inside the standard cell layout, such as the MEOL (middle-end-of-line) and BEOL (back-end-of-line). This parasitic resistance results in poor performance of the standard cell. For example, the response speed of a standard cell unit reduces as the parasitic resistance increases, causing the performance in the response speed of the standard cell element to degrade.
To solve this problem, several new standard cell circuit structures are introduced to reduce parasitic resistance.